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functional block diagram rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 12-bit ultrahigh speed monolithic d/a converter AD568 features ultrahigh speed: current settling to 1 lsb in 35 ns high stability buried zener reference on chip monotonicity guaranteed over temperature 10.24 ma full-scale output suitable for video applications integral and differential linearity guaranteed over temperature 0.3" skinny dip packaging variable threshold allows ttl and cmos interface mil-std-883 compliant versions available product description the AD568 is an ultrahigh-speed, 12-bit digital-to-analog con- verter (dac) settling to 0.025% in 35 ns. the monolithic de- vice is fabricated using analog devices complementary bipolar (cb) process. this is a proprietary process featuring high-speed npn and pnp devices on the same chip without the use of di- electric isolation or multichip hybrid techniques. the high speed of the AD568 is maintained by keeping impedance levels low enough to minimize the effects of parasitic circuit capacitances. the dac consists of 16 current sources configured to deliver a 10.24 ma full-scale current. multiple matched current sources and thin-film ladder techniques are combined to produce bit weighting. the dacs output is a 10.24 ma full scale (fs) for current output applications or a 1.024 v fs unbuffered voltage output. additionally, a 10.24 v fs buffered output may be gen- erated using an onboard 1 k w span resistor with an external op amp. bipolar ranges are accomplished by pin strapping. laser wafer trimming insures full 12-bit linearity. all grades of the AD568 are guaranteed monotonic over their full operating temperature range. furthermore, the output resistance of the dac is trimmed to 100 w 1.0%. the gain temperature coeffi- cient of the voltage output is 30 ppm/ c max (k). the AD568 is available in three performance grades. the AD568jq and kq are available in 24-pin cerdip (0.3") packages and are specified for operation from 0 c to +70 c. the AD568sq features operation from C55 c to +125 c and is also packaged in the hermetic 0.3" cerdip. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 product highlights 1. the ultrafast settling time of the AD568 allows leading edge performance in waveform generation, graphics display and high speed a/d conversion applications. 2. pin strapping provides a variety of voltage and current output ranges for application versatility. tight control of the abso- lute output current reduces trim requirements in externally- scaled applications. 3. matched on-chip resistors can be used for precision scaling in high speed a/d conversion circuits. 4. the digital inputs are compatible with ttl and +5 v cmos logic families. 5. skinny dip (0.3") packaging minimizes board space require- ments and eases layout considerations. 6. the AD568 is available in versions compliant with mil- std-883. refer to the analog devices military products databook or current AD568/883b data sheet for detailed specifications.
model AD568j AD568k AD568s min typ max min typ max min typ max units resolution 12 12 12 bits accuracy 1 linearity C1/2 +1/2 C1/4 +1/4 C1/2 +1/2 lsb t min to t max C3/4 +3/4 C1/2 +1/2 C3/4 +3/4 lsb differential nonlinearity C1 +1 C1/2 +1/2 C1 +1 lsb t min to t max C1 +1 C1 + 1 C1 C1 lsb monotonicity guaranteed over rated specification temperature range unipolar offset C0.2 +0.2 * * * * % of fsr bipolar offset C1.0 +1.0 * * * * % of fsr bipolar zero C0.2 +0.2 * * * * % of fsr gain error C1.0 +1.0 * * * * % of fsr temperature coefficients 2 unipolar offset C5 +5 C3 +3 C5 +5 ppm of fsr/ c bipolar offset C30 +30 C20 +20 C30 +30 ppm of fsr/ c bipolar zero C15+15???? ppm of fsr/ c gain drift C50 +50 C30 +30 C50 +50 ppm of fsr/ c gain drift (i out ) C150 +150 * * * * ppm of fsr/ c data inputs logic levels (t min to t max ) v ih 2.0 7.0****v v il 0.0 0.8 ****v logic currents (t min to t max ) i ih C10 0 +10 *** *** m a i il C0.5 C60 C100 * * * * C100 C200 m a v th pin voltage 1.4 * * v coding binary, offset binary current output ranges 0 to 10.24, 5.12 ma voltage output ranges 0 to 1.024, 0.512 v compliance voltage C2 +1.2 * * * * v output resistance exclusive of r l 160 200 240 * * w inclusive of r l 99 100 101 * * w settling time current to 0.025% 35 * * ns to 0.025% of fsr 0.1% 23 * * ns to 0.1% of fsr voltage 50 w load 3 , 0.512 v p-p, to 0.025% 37 * * ns to 0.025% of fsr to 0.1% 25 * * ns to 0.1% of fsr to 1% 18 * * ns to 1% of fsr 75 w load 3 , 0.768 v p-p, to 0.025% 40 * * ns to 0.025% of fsr to 0.1% 25 * * ns to 0.1% of fsr to 1% 20 * * ns to 1% of fsr 100 w (internal r l ) 3 , 1.024 v p-p, to 0.025% 50 * * ns to 0.025% of fsr to 0.1% 38 * * ns to 0.1% of fsr to 1% 24 * * ns to 1% of fsr glitch impulse 4 350 * * pv-sec peak amplitude 15 * * % of fsr full-scale transltlon 5 10% to 90% rise time 11 * * ns 90% to 10% fall time 11 * * ns power requirements +13.5 v to +16.5 v 27 32 ** * * ma C13.5 v to C16.5 v C7 C8 ** * * ma power dissipation 525 625 * * * * mw psrr 0.05 * * % of fsr/v temperature range rated specification 2 0 +70 0 +70 C55 +125 c storage C65 +150 * * * * c notes *same as AD568j. 1 measured in i out mode. 2 measured in v out mode, unless otherwise specified. see text for further information. 3 total resistance. refer to figure 3, 4 at the major carry, driven by hcmos logic. see text for further explanation. 5 measured in v out mode. specifications shown in boldface are tested on all production units at final electrical test. specifications subject to change without notice. rev. a C2C (@ = +25 8 c, v cc , v ee = 6 15 v unless otherwise noted) AD568Cspecifications
AD568 rev. a C3C ordering guide linearity voltage temperature error max gain t.c. model l package option 2 range 8 c@ 25 8 c max ppm/ 8 c AD568jq 24-lead cerdip (q-24) 0 to +70 1/2 50 AD568kq 24-lead cerdip (q-24) 0 to +70 1/4 30 AD568sq 24-lead cerdip (q-24) C55 to +125 1/2 50 notes 1 for details on grade and package offerings screened in accordance with mil-std-883, refer to the analog devices military products databook or current AD568/883b data sheet. 2 q = cerdip. definitions linearity error (also called integral nonlinear- ity or inl): analog devices defines linearity error as the maximum deviation of the actual analog output from the ideal output (a straight line drawn from 0 to fs) for any bit combina- tion expressed in multiples of 1 lsb. the AD568 is laser trimmed to 1/4 lsb (0.006% of fs) maximum linearity error at +25 c for the k version and 1/2 lsb for the j and s versions. differential linearity error (also called differ- ential nonlinearity or dnl): dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonic behavior warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD568 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. requires that the differential linearity error not exceed 1 lsb in the negative direction. monotonicity: a dac is said to be monotonic if the out- put either increases or remains constant as the digital input increases. unipolar offset error: the deviation of the analog output from the ideal (0 v or 0 ma) when the inputs are set to all 0s is called unipolar offset error. bipolar offset error: the deviation of the analog out- put from the ideal (negative half-scale) when the inputs are set to all 0s is called bipolar offset error. 18 6 7 8 9 10 11 12 1 2 3 4 5 19 20 23 24 13 14 17 2x 4x msb lsb pnp current sources 1.4v band- gap ref threshold control threshold common ladder common pnp switches diffused r-2r ladder (10 - 20 w ) thin-film r-2r ladder (100 - 200 w ) bipolar current generator buried zener reference 21 22 200 w analog common v cc i out reference common 1k w 15 16 load resistor (r l ) bipolar offset (i bpo ) 10v span resistor 10v span resistor i out i out AD568 v ee figure 1. functional block diagram absolute maximum ratings 1 v cc to refcom . . . . . . . . . . . . . . . . . . . . . . . . 0 v to +18 v v ee to refcom . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to C18 v refcom to lcom . . . . . . . . . . . . . . . . . +100 mv to C10 v acom to lcom . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mv thcom to lcom . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mv spans to lcom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v i bpo to lcom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 v i out to lcom . . . . . . . . . . . . . . . . . . . . . . . . . . . C5 v to v th digital inputs to thcom . . . . . . . . . . . . . C500 mv to +7.0 v voltage across span resistor . . . . . . . . . . . . . . . . . . . . . . 12 v v th to thcom . . . . . . . . . . . . . . . . . . . . . . C0.7 v to +1.4 v logic threshold control input current . . . . . . . . . . . . . 5 ma power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mw storage temperature range q (cerdip) package . . . . . . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175 c thermal resistance q ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 c/w q jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 c/w 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configuration
AD568 rev. a C4C their glitch impulse. it is specified as the net area of the glitch in nv-sec or pa-sec. compliance voltage: the range of allowable voltage at the output of a current-output dac which will not degrade the accuracy of the output current. settling time: the time required for the output to reach and remain within a specified error band about its final value, measured from the digital input transition. time ?ns 0.8 0 250 50 output ?volts 100 150 200 0.6 0.4 figure 2. glitch impulse connecting the AD568 unbuffered voltage output unipolar configuration figure 3 shows the AD568 configured to provide a unipolar 0 to +1.024 v output range. in this mode, the bipolar offset termi- nal, pin 21, should be grounded if not used for offset trimming. the nominal output impedance of the AD568 with pin 19 grounded has been trimmed to 100 w , 1%. other output im- pedances can be generated with an external resistor, r ext , be- tween pins 19 and 20. an r ext equalling 300 w will yield a total output resistance of 75 w , while an r ext of 100 w will pro- vide 50 w of output resistance. note that since the full-scale output current of the dac remains 10.24 ma, changing the load impedance changes the unbuffered output voltage accord- ingly. settling time and full-scale range characteristics for these load impedances are provided in the specifications table. bipolar configuration figure 4 shows the connection scheme used to provide a bipolar output voltage range of 1.024 v. the bipolar offset (C0.512 v) occurs when all bits are off (00 . . . 00), bipolar zero (0 v) oc- curs when the msb is on with all other bits off (10 . . . 00), and full-scale minus 1 lsb (0.51175 v) is generated when all bits are on (11 . . . 11). figure 5 shows an optional bipolar mode with a 2.048 v range. the scale factor in this mode will not be as accurate as the configuration shown in figure 4, be- cause the laser-trimmed resistor r l is not used. 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD568 +15v refcom ?5v i bpo r l acom lcom span span thcom vth i out digital inputs 0.2? 0.1? 0.1? 0.1? ?5v +15v analog gnd plane digital gnd plane digital supply ground 100pf r th 1k w +5v analog output r ext (optional) ferrite beads stackpole 57-1392 or amidon fb-43b-101 or equivalent nc nc analog supply ground figure 3. unipolar output unbuffered 0 v to +1.024 v 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD568 +15v refcom ?5v i bpo r l acom lcom span span thcom vth i out digital inputs 0.2? 0.1? 0.1? 0.1? ?5v +15v analog gnd plane digital gnd plane digital supply ground 100pf +5v analog output analog supply ground figure 4. bipolar output unbuffered 0.512 v figure 4 also demonstrates how the internal span resistor may be used to bias the v th pin (pin 13) from a 5 v supply. this eliminates the requirement for an external r th in applications that do not require the precision span resistor. bipolar zero error: the deviation of the analog output from the ideal half-scale output of 0 v (or 0 ma) for bipolar mode when only the msb is on (100 . . .00) is called bipolar zero error. gain error: the difference between the ideal and actual output span of fs C1 lsb, expressed in % of fs, or lsb, when all bits are on. glitch impulse: asymmetrical switching times in a dac give rise to undesired output transients which are quantified by
AD568 rev. a C5C 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD568 +15v refcom ?5v i bpo r l acom lcom span span thcom vth i out digital inputs 0.2? 0.1? 0.1? 0.1? ?5v +15v analog gnd plane digital gnd plane digital supply ground 100pf r th 1k w +5v nc nc analog output analog supply ground figure 5. bipolar output unbuffered 1.024 v optional gan and zero adjustment the gain and offset are laser trimmed to minimize their effects on circuit performance. however, in some applications, it may be desirable to externally reduce these errors further. in those cases, the following procedures are suggested. unipolar mode: (refer to figure 6) step 1 C set all bits (bit 1Cbit 12) to logic 0 (off)note the output voltage. this is the offset error. step 2 C set all bits to logic 1 (on). adjust the gain trim re- sistor so that the output voltage is equal to the desired full scale minus 1 lsb plus the offset error measured in step 1. step 3 C reset all bits to logic 0 (off). adjust the offset trim resistor for 0 v output. 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD568 i bpo r l acom lcom i out digital inputs 5.11k w bit 1 msb bit 12 lsb analog output (0 to 1.024v) 100 w offset gain 20 w figure 6. unbuffered unipolar gain and zero adjust bipolar mode (refer to figure 7) step 1 C set bits to offset binary zero (10 . . . 00). adjust the zero resistor to produce 0 v at the dac output. this removes the bipolar zero error. step 2 C set all bits to logic 1 (on). adjust gain trim resistor so the output voltage is equal to the desired full-scale minus l lsb . step 3 C (optional) if precise trimming of the bipolar offset is preferred to trimming of bipolar zero: set all bits to logic 0 (off). trim the zero resistor to produce the desired negative full scale at the dac output. note: this may slightly compro- mise the bipolar zero trim. 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD568 i bpo r l acom lcom i out digital inputs 5.11k w bit 1 msb bit 12 lsb analog output (?.512 to 0.512v) 75 w gain 20 w 20k w v ee v cc zero figure 7. bipolar unbuffered gain and zero adjust buffered voltage output for full-scale outputs of greater than 1 v, some type of external buffer amplifier is required. the ad840 fills this requirement perfectly, settling to 0.025% from a 10 v full-scale step in less than 100 ns. a 1 k w span resistor has been provided on chip for use as a feedback resistor in buffered applications. using r span (pins 15, 16) introduces a 100 mw code-dependent power source onto the chip which may generate a slight degradation in linearity. maximum linearity performance can be realized by using an ex- ternal span resistor. 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD568 +15v refcom ?5v i bpo r l acom lcom span span thcom vth i out digital inputs 0.2? 0.1? 0.1? 0.1? ?5v +15v analog gnd plane digital gnd plane digital supply ground 100pf +5v analog output analog supply ground 5pf ? s +v s 100 w r th 1k w ad840 amplifier noise gain: 11 figure 8. unipolar output buffered 0 to C10.24v unipolar inverting configuration figure 8 shows the connections for producing a C 10.24 v full- scale swing. this configuration uses the AD568 in the current output mode into a summing junction at the inverting input ter- minal of the external op amp. with the load resistor r l grounded, the dac has an output impedance of 100 w . this produces a noise gain of 11 from the noninverting terminal of the op amp, and hence, satisfies the stability criterion of the ad840 (stable at a gain of 10). the addition of a 5 pf compen-
AD568 rev. a C6C sation capacitor across the 1 k w feedback resistor produces opti- mal settling. lower noise gain can be achieved by connecting r l to i out, increasing the dac output impedance to approximately 200 w , and reducing the noise gain to 6 (illustrated in figure 9). while the output in this configuration will feature improved noise performance, it is somewhat less stable and may suffer from ringing. the compensation capacitance should be in- creased to 7 pf to maintain stability at this reduced gain. 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD568 +15v refcom ?5v i bpo r l acom lcom span span thcom vth i out digital inputs 0.2? 0.1? 0.1? 0.1? ?5v +15v analog gnd plane digital gnd plane digital supply ground 100pf +5v analog output analog supply ground 5pf ? s +v s 100 w r th 1k w ad840 amplifier noise gain: 11 figure 8. unipolar output buffered 0 to C10.24v 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD568 +15v refcom ?5v i bpo r l acom lcom span span thcom vth i out digital inputs 0.2? 0.1? 0.1? 0.1? ?5v +15v analog gnd plane digital gnd plane digital supply ground 100pf +5v analog output analog supply ground 7pf ? s +v s 200 w r th 1k w ad840 amplifier noise gain: 6 figure 9. bipolar output buffered 5.12 v bipolar inverting configuration figure 9 illustrates the implementation of a +5.12 v to C5.12 v bipolar range, achieved by connecting the bipolar offset current, i bpo , to the summing junction of the external amplifier. note that since the amplifier is providing an inversion, the full-scale output voltage is C5.12 v, while the bipolar offset voltage (all bits off) is +5.12 v at the amplifier output. noninverting configuration if a positive full-scale output voltage is required, it can be imple- mented using the AD568 in the unbuffered voltage output mode followed by the ad840 in a noninverting configuration (figure 10). the noise gain of this topology is 10, requiring only 5 pf across the feedback resistor to optimize settling. 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD568 +15v refcom ?5v i bpo r l acom lcom span span thcom vth i out digital inputs 0.2? 0.1? 0.1? 0.1? ?5v +15v analog gnd plane digital supply ground 100pf +5v analog output analog supply ground 5pf ? s +v s 111 w r th 1k w ad840 amplifier noise gain: 10 digital gnd plane figure 10. unipolar output buffered 0 v to +10.24 v guidelines for using the AD568 the designer who seeks to combine high speed with high preci- sion faces a challenging design environment. where tens of milliamperes are involved, fractions of an ohm of misplaced impedance can generate several lsbs of error. increa sing bandwidths make formerly negligible parasitic capacitances and inductances significant. as system performance reaches and ex- ceeds that of the measurement equipment, time-honored test methods may no longer be trustworthy. the dacs placement on the boundary between the analog and digital domains intro- duces additional concerns. proper rf techniques must be used in board design, device selection, supply bypassing, grounding, and measurement if optimal performance is to be realized. the AD568 has been configured to be relatively easy to use, even in some of the more treacherous applications. the device charac- teristics shown in this data sheet are readily achievable if proper attention is paid to the details. since a solid understanding of the circuit involved is one of the designers best weapons against the difficulties of rf design, the following sections provide illus- trations, explanations, examples, and suggestions to facilitate successful design with the AD568. current output vs. voltage output as indicated in figures 3 through 10, the AD568 has been designed to operate in several different modes depending on the external circuit configuration. while these modes may be categorized by many different schemes, one of the most impor- tant distinctions to be made is whether the dac is to be used to generate an output voltage or an output current. in the current output mode, the dac output (pin 20) is tied to some type of summing junction, and the current flowing from the dac into this summing junction is sensed (e.g., figures 8 and 9). in this
AD568 rev. a C7C the threshold of the digital inputs is set at 1.4 v and does not vary with supply voltage. this is provided by a bandgap refer- ence generator, which requires approximately 3 ma of bias cur- rent achieved by tying r th to any +v l supply where r th = + v l 1.4 v 3 ma ? ? ? ? the input lines operate with small input currents to easily achieve interface with unbuffered cmos logic. the digital in- put signals to the dac should be isolated from the analog out- put as much as possible. to minimize undershoot, ringing, and possible digital feedthrough noise, the interconnect distances to the dac inputs should be kept as short as possible. termina- tion resistors may improve performance if the digital lines be- come too long. the digital input should be free from large glitches and ringing and have maximum 10% to 90% rise and fall times of 5 ns. figure 12 shows the equivalent digital input circuit of the AD568. 1.28ma 125 w r th (external) v threshold 1.4v bandgap diode threshold common ladder common to i out to analog common to threshold common +v l 5pf bit input 58pf figure 12. equivalent digital input due to the high-speed nature of the AD568, it is recommended that high-speed logic families such as schottky ttl, high-speed cmos, or the new lines of fast* ttl be used exclusively. table i shows how dac performance can vary depending on the driving logic used. as this table indicates, sttl, hcmos, and fast represent the most viable families for driving the AD568. table i. dac performance vs. drive logic 1 dac 10-90% settling time 2, 3 maximum logic dac 1% 0.1% 0.025% glitch 4 glitch family rise time 2 impulse excursion ttl 11 ns 18 ns 34 ns 50 ns 2.5 nv-s 240 mv lsttl 11 ns 28 ns 46 ns 80 ns 950 pv-s 160 mv sttl 9.5 ns 16 ns 33 ns 50 ns 850 pv-s 150 mv hcmos 11 ns 24 ns 38 ns 50 ns 350 pv-s 115 mv fast* 12 ns 16 ns 36 ns 42 ns 1.0 nv-s 250 mv notes 1 all values typical, taken in rest fixture diagrammed in figure 13. 2 measurements are made for a 1 v full-scale step into 100 w dac load resistance. 3 settling time is measured from the time the digit input crosses the threshold voltage (1.4 v) to when the output is within the specified range of its final value. 4 the worst case glitch impulse, measured on the major carry dac full scale is 1 v. mode, the dac output scale is insensitive to whether the load resistor, r l , is shorted (pin 19 connected to pin 20), or grounded (pin 19 connected to pin 18). however, this does affect the output impedance of the dac current and may have a significant impact on the noise gain of the external circuitry. in the voltage output mode, the dacs output current flows through its own internal impedance (perhaps in parallel with an external impedance) to generate a voltage, as in figures 3, 4, 5, and 10. in this case, the dac output scale is directly dependent on the load impedance. the temperature coefficient of the AD568s internal reference is trimmed in such a way that the drift of the dac output in the voltage output mode is centered on zero. the current output of the dac will have an additional drift factor corresponding to the absolute temperature coeffi- cient of the internal thin-film resistors. this additional drift may be removed by judicious placement of the 1 k w span resistor in the signal path. for example, in figures 8 and 9, the current flowing from the dac into the summing junction could suffer from as much as 150 ppm/ c of thermal drift. however, since this current flows through the internal span resistor (pins 15 and 16) which has a temperature coefficient that matches the dac ladder resistors, this drift factor is compensated and the buffered voltage at the amplifier output will be within specified limits for the voltage output mode. output voltage compliance the AD568 has a typical output compliance range of +1.2 v to C2.0 v (with respect to the lcom pin). the current- steering output stages will be unaffected by changes in the out- put terminal voltage over that range. however, as shown in fig- ure 11, there is an equivalent output impedance of 200 w in parallel with 15 pf at the output terminal which produces an equivalent error current if the voltage deviates from the ladder common. this is a linear effect which does not change with in- put code. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. the positive compliance limit is not affected by the positive power supply, but is a function of output current and the logic threshold voltage at v th , pin 13. i out = 10.24ma x digital in 4096 i out = 10.24ma x digital in 4096 10.24ma r ladder (200 w ) 15pf analog common ladder common r load (200 w ) 15pf compliance to v threshold r load i out r ladder (200 w ) compliance to logic low value ( 1 ? ) figure 11. equivalent output digital input considerations the AD568 uses a standard positive true straight binary code for unipolar outputs (all 1s full-scale output), and an offset bi- nary code for bipolar output ranges. in the bipolar mode, with all 0s on the inputs, the output will go to negative full scale; with 111 . . . 11, the output will go to positive full scale less 1 lsb; and with 100 . . 00 (only the msb on), the output will go to zero.
AD568 rev. a C8C the variations in settling times can be attributed to differences in the rise time and current driving capabilities of the various families. differences in the glitch impulse are predominantly de- pendent upon the variation in data skew. variations in these specs occur not only between logic families, but also between different gates and latches within the same family. when select- ing a gate to drive the AD568 logic input, pay particular atten- tion to the propagation delay time specs: t plh and t phl . selecting the smallest delays possible will help to minimize the settling time, while selection of gates where t plh and t phl are closely matched to one another will minimize the glitch impulse resulting from data skew. of the common latches, the 74374 oc- tal flip-flop provides the best performance in this area for many of the logic families mentioned above. *fast is a registered trademark of fairchild camera and instrumentation corporation. 1a 1b 2a 2b 3a 3b 4a 4b v cc 1v 2v 3v 4v strobe gnd 1a 1b 2a 2b 3a 3b 4a 4b v cc 1v 2v 3v 4v strobe gnd 1a 1b 2a 2b 3a 3b 4a 4b v cc 1v 2v 3v 4v strobe gnd 1 2 3 4 5 6 7 8 9 10 11 12 v cc refcom acom thcon v ee i bpo i out r l r span v th lcom r span AD568 +15v ?5v v out 1k +5v +5v clock in word a 12 12 word b select 74158 select 74158 select 74158 figure 13. test setup for glitch impulse and settling time measurements settling time considerations as can be seen from table i and the specifications page, the set- tling time of the AD568 is application dependent. the fastest settling is achieved in the current-output mode, since the volt- age output mode requires the output capacitance to be charged to the appropriate voltage. the dacs relatively large output current helps to minimize this effect, but settling-time sensitive applications should avoid any unnecessary parasitic capacitance at the output node of voltage output configurations. direct mea- surement of the fine scale dac settling time, even in the voltage output mode, is extremely tricky: analog scope front ends are generally incapable of recovering from overdrive quickly enough to give an accurate settling representation. the plot shown in figure 14 was obtained using data precisions 640 16-bit sam- pling head, which features the quick overdrive recovery charac- teristic of sampling approaches combined with high accuracy and relatively small thermal tail. time ?ns 0 120 20 dac output ?volts 40 60 80 100 1.026 1.024 1.022 figure 14. zero to full-scale settling glitch considerations in many high-speed dac applications, glitch performance is a critical specification. in a conventional dac architecture such as the AD568 there are two basic glitch mechanisms: data skew and digital feedthrough. a thorough understanding of these sources can help the user to minimize glitch in any application. digital feedthroughas with any converter product, a high-speed digital-to-analog converter is forced to exist on the frontier between the noisy environment of high-speed digital logic and the sensitive analog domain. the problems of this in- terfacing are particularly acute when demands of high speed (greater than 10 mhz switching times) and high precision (12 bits or more) are combined. no amount of design effort can perfectly isolate the analog portions of a dac from the spectral components of a digital input signal with a 2 ns risetime. inevi- tably, once this digital signal is brought onto the chip, some of its higher frequency components will find their way to the sensi- tive analog nodes, producing a digital feedthrough glitch. to minimize the exposure to this effect, the AD568 has intention- ally omitted the on-board latches that have been included in many slower dacs. this not only reduces the overall level of digital activity on chip, it also avoids bringing a latch clock pulse on board, whose opposite edge inevitably produces a substantial glitch, even when the dac is not supposed to be changing codes. another path for digital noise to find its way onto a con- verter chip is through the reference input pin. the completely internal reference featured in the AD568 eliminates this noise input, providing a greater degree of signal integrity in the analog portions of the chip. data skewthe AD568, like many of its slower predeces- sors, essentially uses each digital input line to switch a separate, weighted current to either the output (i out ) or some other node (analog com). if the input bits are not changed simulta- neously, or if the different dac bits switch at different speeds, then the dac output current will momentarily take on some in- correct value. this effect is particularly troublesome at the carry points, where the dac output is to change by only one lsb, but several of the larger current sources must be switched to realize this change. data skew can allow the dac output to move a substantial amount towards full scale or zero (depending upon the direction of the skew) when only a small transition is desired. great care was taken in the design and layout of the AD568 to ensure that switching times of the dac switches are symmetrical and that the length of the input data lines are short
AD568 rev. a C9C and well matched. the glitch-sensitive user should be equally diligent about minimizing the data skew at the AD568s inputs, particularly for the 4 or 5 most significant bits. this can be achieved by using the proper logic family and gate to drive the dac, and keeping the interconnect lines between the logic out- puts and the dac inputs as short and as well matched as pos- sible, particularly for the most significant bits. the top 6 bits should be driven from the same latch chip if latches are used. glitch reduction schemes bit-deskewingeven carefully laid-out boards using the proper driving logic may suffer from some degree of data-skew induced glitch. one common approach to reducing this effect is to add some appropriate capacitance (usually several pf) to each of the 2 or 3 most significant bits. the exact value of each capacitor for a given application should be determined experi- mentally, as it will be dependent on circuit board layout and the type of driving logic used. table ii presents a few examples of how the glitch impulse may be reduced through passive deskewing. table ii. bit delay glitch reduction examples 1 logic uncompensated compensation compensated family gate glitch used glitch hcmos 74157 350 pv-s c2 = 5 pf 250 pv-s sttl 74158 850 pv-s r1 = 50 w , 600 pv-s c1 = 7 pf note 1 measurements were made using a modified version of the fixture shown in figure 13, with resistors and capacitors placed as shown in figure 15. resis- tance and capacitance values were set to zero except as noted. as figure 15 indicates, in some cases it may prove useful to place a few hundred ohms of series resistance in the input line to enhance the delay effect. this approach also helps to reduce some of the digital feedthrough glitch, as the higher frequency spectral components are being filtered out of the most signifi- cant bits digital inputs. 1 2 3 4 5 6 r1 r2 r3 from driving logic bit 1 (msb) bit 2 bit 3 bit 4 bit 5 bit 6 AD568 r ?c bit deskewing scheme figure 15. r-c bit deskewing scheme threshold shiftit is also possible to reduce the data skew by shifting the level of logic voltage threshold, v th (pin 13). this can be readily accomplished by inserting some resis- tance between the threshold com pin (pin 14) and ground, as in figure 16. to generate threshold voltages below 1.4 v, pin 13 may be directly driven with a voltage source, leav- ing pin 14 tied to the ground plane. as note 2 in table iii indi- cates, lowering the threshold voltage may reduce output voltage compliance below the specified limits, which may be of concern in an unbuffered voltage output topology. 14 13 +5v ra rb thcom v th c1 AD568 c1: 1000pf chip capacitor analog ground plane figure 16. positive threshold voltage shift table iii shows the glitch reduction achieved by shifting the threshold voltage for hcmos, sttl, and fast logic. table iii. threshold shift for glitch improvement 1 logic uncompensated modified resulting family gate glitch threshold 2 glitch hcmos 74hc158 350 pv-s 1.7 v 150 pv-s sttl 74s158 850 pv-s 1.0 v 200 pv-s fast 74f158 1000 pv-s 1.3 v 480 pv-s notes 1 measurements made on a modified version of the circuit shown in figure 13, with a 1 v full scale. 2 use care in any scheme that lowers the threshold voltage since the output volt- age compliance of the dac is sensitive to this voltage. if the dac is to be op- erating in the voltage output mode, it is strongly suggested that the threshold voltage be set at least 200 mv above the output voltage full scale. deglitching some applications may prove so sensitive to glitch impulse that reduction of glitch impulse by an order of magnitude or more is required. in order to realize glitch impulses this low, some sort of sample-and-hold amplifier (sha)-based deglitching scheme must be used. there are high-speed shas available with specifications suffi- cient to deglitch the AD568, however most are hybrid in design at costs which can be prohibitive. a high performance, low cost alternative shown in figure 17 is a discrete sha utilizing a high-speed monolithic op amp and high-speed dmos fet switches. this sha circuit uses the inverting integrator architecture. the ad841 operational amplifier used (300 mhz gain bandwidth product) is fabricated on the same high-speed process as the AD568. the time constant formed by the 200 w resistor and the 100 pf capacitor determines the acquisition time and also band limits the output signal to eliminate slew induced distortion. a discrete drive circuit is used to achieve the best performance from the sd5000 quad dmos switch. this switch driving cell is composed of mps571 rf npn transistors and an mc10124 ttl to ecl translator. using this technique provides both high speed and highly symmetrical drive signals for the sd5000 switches. the switches are arranged in a single-throw double- pole (spdt) configuration. the 360 pf flyback capacitor is switched to the op amp summing junction during the hold mode to keep switching transients from feeding to the output. the ca- pacitor is grounded during sample mode to minimize its effect on acquisition time.
AD568 rev. a C10C circuit layout for a high speed sha is almost as critical as the design itself. figure 17 shows a recommended layout of the deglitching cell for a double sided printed circuit board. the layout is very compact with care taken that all critical signal paths are short. ?v mc 10124 249 w 169 w 510 w 360 w 360 w ?v 169 w 249 w 500pf output 75 w 200 w 200 w in4735 +15v ?5v ?5v 20k w 1.6 w 0.39? to pin 2 sd5000 100pf 4 5 10 11 9 16 14 13 12 6 8 5 4 3 1 ad841 figure 17. high performance deglitcher grounding rules the AD568 brings out separate reference, output, and digital power grounds. this allows for optimum management of signal ground currents for low noise and high-speed-settling perfor- mance. the separate ground returns are provided to minimize changes in current flow in the analog signal paths. in this way, logic return currents are not summed into the same return path with the analog signals. it is important to understand which supply and signal currents are flowing in which grounds so that they may be returned to the proper power supply in the best possible way. the majority of the current that flows into the v cc supply (pin 24) flows out (depending on the dac input code) either the analog common (pin 18), the ladder common (pin 17), and/or i out (pin 20). the current in the ladder common is configured to be code independent when the output current is being summed into a virtual ground. if i out is operated into its own output im- pedance (or in any unbuffered voltage output mode) the current in ladder common will become partially code dependent. the current in the analog common (pin 18) is an ap- proximate complement of the current in i out , i.e., zero when the dac is at full scale and approximately 10 ma at zero input code. a relatively constant current (not code dependent) flows out the reference common (pin 23). the current flowing out of the v ee supply (pin 22) comes from a combination of reference ground and bipolar offset (pin 21). the plus and minus 15 v supplies are decoupled to the reference common. the ground side of the load resistor r l , analog common and ladder common should be tied together as close to the package pins as possible. the analog output voltage is then referred to this node and thus it becomes the high quality ground for the AD568. the reference common (and bipolar offset when not used), should also be connected to this node. all of the current that flows into the v th terminal (pin 13) from the resistor tied to the 5 v logic supply (or other convenient positive supply) flows out the threshold common (pin 14). this ground pin should be returned directly to the digital ground plane on its own individual line. the +5 v logic supply should be decoupled to the thresh- old common. because the v th pin is connected directly to the dac switches it should be decoupled to the analog output signal common. in order to preserve proper operation of the dac switches, the digital and analog grounds need to eventually be tied together. this connection between the ground planes should be made within 1/2" of the dac. the use of ground and power planes if used properly, ground planes can perform a myriad of func- tions on high-speed circuit boards: bypassing, shielding, current transport, etc. in mixed signal design, the analog and digital por- tions of the board should be distinct from one another, with the analog ground plane covering analog signal traces and the digital ground plane confined to areas covering digital interconnect. the two ground planes should be connected at or near the dac. care should be taken to insure that the ground plane is uninterrupted over crucial signal paths. on the digital side, this includes the digital input lines running to the dac and any clock lines. on the analog side, this incudes the dac output signal as well as the supply feeders. the use of side runs or planes in the routing of power lines is also recommended. this serves the dual function of providing a low series impedance power supply to the part as well as providing some free ca- pacitive decoupling to the appropriate ground plane. figure 18 illustrates many of the points discussed above. if more layers of interconnect are available, even better results are possible. using the right bypass capacitors probably the most important external components associated with any high-speed design are the capacitors used to bypass the power supplies. both selection and placement of these ca- pacitors can be critical and, to a large extent, dependent upon the specifics of the system configurations. the dominant consid- eration in selection of bypass capacitors for the AD568 is mini- mization of series resistance and inductance. many capacitors will begin to look inductive at 20 mhz and above, the very fre- quencies we are most interested in bypassing. ceramic and film- type capacitors generally feature lower series inductance than tantalum or electrolytic types. a few general rules are of univer- sal use when approaching the problem of bypassing: bypass capacitors should be installed on the printed circuit board with the shortest possible leads consistent with reliable construction. this helps to minimize series inductance in the leads. chip capacitors are optimal in this respect. some series inductance between the dac supply pins and the power supply plane often helps to filter out high-frequency power supply noise. this inductance can be generated using a small ferrite bead.
AD568 rev. a C11C 5v digital ground plane clock analog ground plane +15v ?5v output 5v input words AD568 settling/glitch evaluation board component side analog +5v +5v analog v cc analog v ee foil side figure 18. printed circuit board layout high-speed interconnect and routing it is essential that care be taken in the signal and power ground circuits to avoid inducing extraneous voltage drops in the signal ground paths. it is suggested that all connections be short and direct, and as physically close to the package as possible, so that the length of any conduction path shared by external compo- nents will be minimized. when runs exceed an inch or so in length, some type of termination resistor may be required. the necessity and value of this resistor will be dependent upon the logic family used. for maximum ac performance, the dac should be mounted di- rectly to the circuit board; sockets should not be used as they in- troduce unwanted capacitive coupling between adjacent pins of the device. applications 1 m s, 12-bit successive approximation a/d converter the AD568s unique combination of high speed and true 12-bit accuracy can be used to construct a 12-bit sar-type a/d con- verter with a sub- m s conversion time. figure 19 shows the con- figuration used for this application. a negative analog input voltage is converted into current and brought into a summing junction with the dac current. this summing junction is bidirectionally clamped with two schottky diodes to limit its voltage excursion from ground. this voltage is differentially am- plified and passed to a high-speed comparator. the comparator output is latched and fed back to the successive approximation register, which is then clocked to generated the next set of codes for the dac. 13 16 15 14 24 23 22 21 20 19 18 17 +15v refcom ?5v i bpo r l acom lcom span span thcom v th i out 12 11 10 9 8 1 2 3 4 7 6 5 dac AD568 0.2? 0.1? 0.1? 0.1? ?5v +15v analog gnd plane 100pf 1k +5v nc nc 4 7 6 5 21 20 19 18 17 16 9 8 q11 q10 q9 q8 q6 q5 q4 q3 q2 q1 q0 q7 11 3 14 1 13 24 12 2 23 22 15 10 v cc gnd d0 q 11 nc nc cp e s cc d nc +5v parallel data out sar 2504 0.01? 1k 620 620 2.5k v i 0 to ?0.24v n +5v ?v ?v 1k 150 q1 q2 q3 d1 d2 27k ?5v 1 2 3 4 8 7 6 5 v+ +in v ?n out out lch gnd comparator lt1016 d3 in4148 conversion complete start comvert chip enable 150k w +5v inverter 74hc04 15k w 150k w q4 q5 figure 19. AD568 1 m s successive approximation a/d application
AD568 rev. a C12C circuit details figure 20 shows an approximate timing budget for the a/d con- verter. if 12 cycles are to be completed in 1 m s, approximately 80 ns is allowed for each cycle. since the schottky diodes clamp the voltage of the summing junction, the dac settling time ap- proaches the current-settling value of 35 ns, and hence uses up less than half the timing budget. to maintain simplicity, a simple clock is used that runs at a constant rate throughout the conversion, with a duty cycle of approximately 90%. if absolute speed is worth the additional complexity, the clock frequency can be increased as the conver- sion progresses since the dac must settle from increasingly smaller steps. when seeking a cycle time of less than 100 ns, the delays gener- ated by the older generation sar registers become problematic. newer, high speed sar logic chips are becoming available in the classic 2504 pinout that cuts the logic overhead in half. one example of this is zyrels zr2504. finding a comparator capable of keeping up with this dac ar- rangement is fairly difficult: it must respond to an overdrive of 250 m v (1 lsb) in less than 25 ns. since no inexpensive com- parator exists with these specs, special arrangements must be made. the lt106 comparator provides relatively quick re- sponse, but requires at least 5 mv of overdrive to maintain this speed. a discrete preamplifier may be used to amplify the sum- ming junction voltage to sufficiently overdrive the comparator. care must be exercised in the layout of the preamp/comparator block to avoid introducing comparator instability with the preamps additional gain. 10ns 35ns 15ns 10ns 10ns 0 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns clock pulse start of next clock cycle latch comparator start of clock cycle sar delay dac settling preamp delay comparator delay figure 20. typical clock cycle for a 1 m s sar a/d converter high-speed multiplying dac a powerful use for the AD568 is found in multiplying applica- tions, where the dac controls the amplitude of a high-speed signal. specifically, using the AD568 as the control voltage input signal for the ad539 60 mhz analog multiplier and ad5539 wideband op amp, a high-speed multiplying dac can be built. in the application shown in figure 21, the AD568 is used in a buffered voltage output mode to generate the input to the ad539s control channel. the speed of the AD568 allows oversampling of the control signal waveform voltage, thereby providing increased spectral purity of the amplitude envelope that modulates the analog input channels. the AD568 is configured in the unbuffered unipolar output mode. the internal 200 w load resistor creates the 0-1 v fs output signal, which is buffered and amplified to a 0-3 v range suitable for the control channel of the ad539. a 500 w input impedance exists at pin 1, the input channel. to provide a buffer for the 0-1 v output signal from the AD568 looking into the impedance and to achieve the full-scale range, the ad841, high-speed, fast settling op amp is included. the gain of 3 is achieved with a 2 k w resistor configured in follower mode with a 1 k w pot and 500 w resistor. a 20 k w pot with connections to pins 3, 4 and 12 is provided for offset trim. the ad539 can accept two separate input signals, each with a nominal full-scale voltage range of 2 v. each signal can then be simultaneously controlled by the AD568 signal at the com- mon input channels, pins 11 and 14, applied to the ad5539 in a subtracting configuration, provide the voltage output signal: v out = d 4096 v y 1 v y 2 2 v (0 d 4095) for applications where only a single channel is involved, chan- nel 2, v y2 , is tied to ground. this provides: v out = d 4096 v y 1 2 v (0 d 4095) some ad539 circuit details: the control amplifier compensa- tion capacitor for pin 2, c c , must have a minimum value of 300 pf to provide circuit stability. for improved bandwidth and feedthrough, the feedthrough capacitor between pins 1 and 2 should be 5-20% of c c . a schottky diode at pin 2 can improve recovery time from small negative values of v x . lead lengths along the path of the high-speed signal from AD568 should be kept at a minimum.
AD568 rev. a C13C 16 15 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD568 +15v refcom ?5v i bpo r l acom lcom span span thcom vth i out digital inputs 0.2? 0.1? 0.1? 0.1? ?5v +15v analog gnd plane digital gnd plane digital supply ground 100pf r th 1k w +5v nc nc analog output analog supply ground 4 3 10 12 6 5 c ff 100pf c c 3000pf 75 w 1? 1? ? s 20k w ad841 2k w 1k w 500 w +v s 13 14 1 2 3 4 5 6 7 8 9 10 11 12 AD568 w1 z1 ch1 output base common z2 w2 ch2 output 11 +v s ? s control hf comp ch1 input input common output common ch2 input v x 75 w v y1 in v y1 in 10 w 10 w +9v ?v 200 w gain adjust ( 4% range) 10 7 1 14 ?v ad5539n 8 100k 180 w 470 w 2.7 w 0.47? ?v 50k (optional) output offset ?v +9v +9v 0.47? 2.7 w v out 3 d1 180 w c f 0.25pf 1.5pf d1: thompson csfbar ?10 or similar schottky diode short, direct connection to ground plane. figure 21. wideband digitally controlled multiplier outline dimensions dimensions shown in inches and (mm). 24-pin cerdip (suffix q)
c1014aC9C7/87 printed in u.s.a. C14C

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